Embodiments of the present invention related in general to instruction sequencing in an out-of-order (OoO) processor, and more specifically to wide vector execution in a single thread mode for an out-of-order processor.
In an out-of-order (OoO) processor, an instruction sequencing unit (ISU) dispatches instructions to various issue queues, renames registers in support of OoO execution, issues instructions from the various issue queues to the execution pipelines, completes execution instructions, and handles exception conditions. Register renaming is typically performed by mapper logic in the ISU before the instructions are placed in their respective issue queues.